 K=9
(256 states).
Rates
½ and 1/3. Other rates can be supplied by external puncturing.
Parameterizable
soft inputs.
Parameterizable
convergence traceback length.
On
the fly configurable traceback length.
Variable
algorithm radix to support low to high thorughput, 10-170Mbps
on FPGA device.
Zero
delay between packets.
Generator
polynomials:
G0=557(octal), G1=663(octal),
G2=711(octal) (rate 1/3).
G0=561(octal), G1=753(octal)
(rate ½).
All-synchronous
design using a single clock, except for global asynchronous reset.
Simple
interface.
Available
as verilog source code or as netlist.
BER
of 10^-7 at 4.5 dB.
Silicon
proven, FPGA proven.
Ordering information
Viterbi K=9 decoder available as verilog source code or as EDIF
netlist.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Verilog
testing environment.
Bit-exact
Matlab model.
Documentation.
For more information please
contact
us
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