 K=7
(64 states) G0=133(octal), G1=165(octal), G2=171(octal).
Rate
1/3. Other rates can be supplied by external puncturing.
Supports
WiMAX Viterbi decoding.
Parameterizable
algorithm radix, 2 or 4.
Supports
tail biting.
Parameterizable
soft input width.
Parameterizable
traceback length (memory depth).
On
the fly configurable traceback length, to support low latency.
Memory
type (SRAM / register file), supports Altera/Xilinx coding style
for easy synthesis.
Optional
controls (decoder_en - for discontinuous data stream, decoder_abort
- to reset the decoder).
Supports
low power features (clock gating, grey decoding, ...)
Area/Power
efficient architecture utilizing RAM for trace back storage.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available
as verilog source code or as netlist.
Silicon
proven, FPGA proven.
Decoder performance
Delay and throughput of the decoder are available with our free
Viterbi delay calculator:
Download Viterbi decoder
delay calculator 
Ordering information
Viterbi K=7 decoder available as verilog source code or as EDIF
netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Extensive
testing environment (test bench + stimuli generator).
Matlab
model.
Synthesis
script for Synopsys Design Compiler
Detailed
documentation.
For more information please contact
us
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