 K=7
(64 states) G1=171(octal), G2=133(octal), G3=165(octal), G4=117(octal),
G5=127(octal).
Rate
1/5. Other rates can be supplied by external puncturing.
Support
WiMAX rate 1/2 and LTE rate 1/3 Viterbi decoding.
Parameterizable
algorithm radix, 2 or 4.
Parameterizable
soft input width.
Parameterizable
traceback length (memory depth).
On
the fly configurable traceback length, to support low latency.
Supports
low power features.
Area/Power
efficient architecture utilizing RAM for trace back storage.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available
as verilog source code or as netlist.
Decoder performance
Delay and throughput of the decoder are available with our free
Viterbi delay calculator:
Download Viterbi decoder
delay calculator 
Ordering information
Viterbi K=7 decoder available as verilog source code or as EDIF
netlist.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Extensive
testing environment.
Bit-exact
Matlab model.
Detailed
documentation.
For more information please contact
us
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