 K=7
(64 states), G0=171(octal), G1=133(octal).
Rate
½. Other rates can be supplied by external puncturing.
Parameterizable
algorithm radix, 2 or 4.
Parameterizable
soft input width.
Parameterizable
trace back length.
On
the fly configurable trace back length, to support low latency.
Supports
tail biting.
Throughput
> 155 Mbit/sec on FPGA (with both radix 2 or radix 4 versions).
Area/Power
efficient architecture utilizing RAM for trace back storage.
Memory
type (SRAM / register file), supports Altera/Xilinx coding style
for easy synthesis.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available
as verilog source code or as netlist.
Silicon
proven and FPGA proven several times.
Decoder performance
Delay and throughput of the decoder are available with our free
Viterbi delay calculator:
Download Viterbi decoder
delay calculator 
Performance graph
Viterbi
decoder bit error rate performance in BPSK AWGN channel
Ordering information
Viterbi K=7 decoder available as verilog source code or as EDIF
netlist.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Extensive
testing environment.
Bit-exact
Matlab model.
Detailed
documentation.
For more information please contact
us
Back to top
|
