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Compiler features:
 Support
any constraint length (K), Parameterizable polynomials.
Support
any rate, any number of polynomials.
Parameterizable
algorithm radix, 2, 4 or 8.
Parameterizable
soft input width.
Parameterizable
traceback length (memory depth).
On
the fly configurable traceback length, to support low latency.
On
the fly configurable termination method (tail-biting, zeros tail
bits, partial zeros tail bits).
Zero
delay between packets.
Memory
type (SRAM / register file), supports Altera/Xilinx coding style
for easy synthesis.
Supports
low power features (clock gating, grey decoding, ...)
Compiler
outputs are Viterbi decoder HDL + test bench.
All-synchronous
design using a single clock, except for global asynchronous reset.
Silicon
proven. FPGA proven.
Typical
applications - WiMAX (802.16d/e/m), 3GPP (WCDMA/HSPA/LTE), GSM,
DVB, and more.
Typical
throughput of 100Mbps-1Gbps.
For more information please
contact
us
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