Key Features:
 Code
length: 648, 1296, 1944.
Code
rates: 1/2, 2/3, 3/4, 5/6 (for each code length).
Supports
shortening, puncturing and repetition as defined in the standard.
Code
synthesizable to ASIC and FPGA.
Ordering information
802.11ac/n LDPC encoder available as verilog/VHDL source code
or as EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog/VHDL
source code or verilog EDIF netlist.
Extensive
testing environment (test bench + stimuli generator).
Matlab
model.
Synthesis
script for Synopsys Design Compiler
Detailed
documentation.
For more information please contact
us
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