The IEEE 802.11ac/n LDPC Decoder Core
performs iterative decoding of channel data that has been encoded
as described in the IEEE Std 802.11ac and 802.11n standard.
Key Features:
 Code
length: 648, 1296, 1944.
Code
rates: 1/2, 2/3, 3/4, 5/6 (for each code length).
Programmable
number of iterations.
Syndrome
based LDPC iteration stopping and indication.
High
throughput support - up to 1.732Gbps.
Based
on proprietary architecture, to reach high throughput with low
area.
Built
in power saving fetures for low power design.
Code
synthesizable to ASIC and FPGA.
Ordering information
802.11ac/n LDPC decoder available as verilog/VHDL source code
or as EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog/VHDL
source code or verilog EDIF netlist.
Extensive
testing environment (test bench + stimuli generator).
Matlab
model.
Synthesis
script for Synopsys Design Compiler
Detailed
documentation.
For more information please contact
us
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