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 Supports
CCM, VCM, ACM modes.
Supports 64Kbit
and 16Kbit frames.
0.1dB to 0.5dB coding
gain improvement versus the standard reference.
Frame by frame programmability
of code rate, modulation, block size, number of iterations.
Syndrome based LDPC
iteration stopping and indication.
Includes internal
demodulator and standard interleaver.
Relative low area.
Low power design.
fits both FPGA and
ASIC technologies.
Silicon proven.
Ordering information
DVB-S2 LDPC decoder available as verilog source code.
Delivery includes:
Verilog
source code (optional VHDL).
Extensive
test bench environment.
C/Matalb
bit accurate model.
Detailed
documentation.
For more information please contact
us
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