 Rates
1/3, 1/2 and 2/3.
Compliant with TETRA-TEDS
specifications.
Block length up
to 6144.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available
as verilog source code or as netlist.
Based
on our silicon/FPGA proven 3GPP Turbo encoder.
download
product brief 
Ordering information
Turbo code encoder available as verilog source code or as EDIF
netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Verification
environment.
Matlab
model.
Documentation.
For more information please
contact
us
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