 K=4
(8 states).
Rates 1/3, 1/2 and
2/3.
Up to 18.5 Mbps
with 5 full iterations with Altera Stratix4 FPGA family.
Sophisticated early
termination mechanism to support power saving and higher statistical
throughput.
Compliant with TETRA-TEDS
specifications.
Block length up
to 6144.
Block-by-block change
of block size / number of iterations.
Soft
input width parameter (pre-synthesis).
All-synchronous
design using a single clock, except for global asynchronous reset.
Simple processor
interface for easy programming of configuration registers.
Available
as verilog source code or as netlist.
Based
on our silicon/FPGA proven 3GPP Turbo decoder.
Optional
Viterbi K=5 rate 1/4 decoder (defined in the TETRA standard).
download
product brief 
Turbo code decoder general diagram
Implementation
The base decoder is Max Log MAP with LLR scaling. This decoder
gives only -0.1 dB performance compared with MAP/log MAP decoders,
but ~40% smaller.
Ordering information
Turbo Code decoder available as verilog source code or as EDIF
netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Extensive
Verilog testing environment + stimuli generator.
Bit-exact
Matlab model.
Detailed
documentation.
For more information please contact
us
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