 Rate
1/3, other rates can be achieved with external puncturing.
Implements the 3GPP
LTE specification.
Core contains the
full 3GPP LTE interleaver.
All 188 3GPP LTE
block sizes (40 - 6144) supported.
No internal memory
is needed.
All-synchronous
design using a single clock, except for global asynchronous reset.
Simple processor
interface for easy programming of configuration registers.
Available as verilog
(optional VHDL) source code or as netlist.
download
product brief
Turbo
code encoder general diagram
The polynomial described in this
implementation is:
The encoder transmits two parity channels and one common (systematic)
channel.
Termination issue
Termination is performed by taking the tail bits from the shift
register feedback after all information bits are
encoded. Tail bits are padded after the encoding of information
bits.
The first three tail bits shall be used to terminate the first
constituent encoder (upper switch of the figure above in lower
position) while the second constituent encoder is disabled. The
last three tail bits shall be used to terminate the second
constituent encoder (lower switch of the figure above in lower
position) while the first constituent encoder is disabled.
The transmitted bits for trellis termination shall then be:
xK+1, zK+1, xK+2, zK+2, xK+3, zK+3, x'K+1, z'K+1, x'K+2, z'K+2,
x'K+3, z'K+3..
Ordering information
LTE Turbo code encoder available as verilog source code or as
EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog/VHDL
source code or verilog EDIF netlist.
Verification
environment.
Matlab
model.
Documentation.
For more information please
contact
us
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