 Rate
1/3, other rates can be achieved with external puncturing.
Implements the 3GPP
Long Term Evolution (LTE) specification.
Core contains the
full 3GPP LTE interleaver.
All 188 3GPP LTE
block sizes (40 - 6144) supported.
Dynamically selectable
number of Iterations.
Scalable decoder
architecture, to support various throughput targets, from low
to ultra high at constant number of iterations (400Mbps, technology
dependent).
Sophisticated early
termination mechanism to support power saving and higher statistical
throughput.
Novel architecture
reaches higher throughput per silicon size compared to competitors
solution.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available as verilog
(optional VHDL) source code or as netlist.
Silicon
proven and FPGA proven.
download
product brief
Turbo code decoder general diagram
Implementation
The base decoder is Max Log MAP with LLR scaling. This decoder
gives only -0.1 dB performance compared with MAP/log MAP decoders,
but ~40% smaller.
Ordering information
LTE Turbo Code decoder available as verilog source code or as
EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog/VHDL
source code or verilog EDIF netlist.
Extensive
Verilog testing environment.
Bit-exact
Matlab model.
Detailed
documentation.
For more information please contact
us
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